1. Field of the Invention
The present invention relates to semiconductor memory devices having the data input/output operation controlled by an input/output control signal applied via a buffer circuit. More particularly, the present invention relates to a dynamic semiconductor memory device including an CMOS buffer circuit receiving an input/output control signal for rewriting stored information according to a refresh operation.
2. Description of the Background Art
In recent years, increase in speed and reduction in consumption power are important factors in semiconductor memory devices, particularly in an DRAM (Dynamic Random Access Memory). Reduction in the standby current when operated by the power of a battery is particularly regarded as an important factor.
In an DRAM, a standby current refers to the consumed current when power supply potentials V.sub.cc and V.sub.ss are applied to drive a row strobe signal (/RAS signal) and a column strobe signal (/CAS signal) which are control signals to an H level (logical high). According to the product standards, the level of input pins other than those of signals /RAS and /CAS are arbitrary.
Data input/output between an DRAM and the outside world is controlled by a write enable signal (/WE signal) which is an external control signal for a writing operation and an output enable signal (/OE signal) which is an external control signal for a readout operation. These external input/output signals are transmitted to an DRAM internal circuit via an input buffer circuit of an CMOS circuit.
Since the level of the input pins of these external input/output control signals are arbitrary in the above mentioned stand-by state, a through current will flow to the CMOS circuit to increase power consumption if the potential level of these pins attains an intermediate level of an H level and an L level (logical low) of the CMOS circuit.
The above problem will be described in more detail hereinafter.
FIG. 5 shows a first conventional implement of a first stage input buffer of signal /WE or a signal /OE. In the following description of the operation of the buffer circuit, an external write enable signal and an external output enable signal are represented as EXTZWE and EXTZOE, respectively, and an internal write enable signal and an internal output enable signal are represented as ZWEF and ZOEF, respectively, to distinguish an external input/output control signal from an internal input/output control signal passed through an input buffer circuit.
Signal EXTZWE is applied to the other input terminal of an NOR circuit 216 having one input terminal fixed to an L level. Therefore, the output signal of NOR circuit 216 is an inverted version of signal EXTZWE. This output signal is applied to a half latch circuit formed of a P channel MOS transistor 312 and an inverter 314 to have its value maintained. The output of this latch circuit is applied to a drive circuit formed of inverters 316 and 318 to be output as signal ZWEF.
External input/output control signal EXTZOE is transmitted in a manner identical to the above.
FIG. 11 shows an example of a structure of NOR circuit 216.
NOR circuit 216 includes P channel MOS transistors 220 and 222 connected in series between power supply potential V.sub.cc corresponding to an H level and power supply potential V.sub.ss corresponding to an L level, and N channel MOS transistors 226 and 224 connected in parallel to P channel MOS transistors 220 and 222.
In the first conventional implement of FIG. 5, signal S which is one input signal of NOR circuit 216 is fixed to the L level. Therefore, P channel MOS transistor 220 is always conductive. When signal EXTZWE attains an intermediate potential level, a through current will flow via P channel MOS transistors 220 and 222 and N channel MOS transistor 224.
FIG. 6 shows a second implement of an input buffer circuit of signal /WE or /OE directed to prevent generation of the above-described through current during a self refresh operation.
A memory cell of an DRAM generally has a structure of storing information by means of charge in a capacitor.
Therefore, charge stored in the capacitor due to a writing operation of data is gradually drawn out by various leakage such as a subthreshold current of an access transistor. It is therefore necessary to carry out a refresh operation of reading out and then rewriting the data again before the stored information is completely lost.
A refresh operation interrupting a random access operation of reading/writing and a refresh operation carried out only for maintaining the stored information in the chip such as during a battery backup term are known. A CBR (/CAS before/RAS) refresh operation, for example, is typical of the former. Also, a self refresh operation is typical of the latter.
It is possible to suppress generation of a through current in an input buffer circuit during a self refresh period by inactivating the above-described external input/output control signal input buffer circuit only during this self refresh period by a signal having its level changed.
In the second implement shown in FIG. 6, signal ZBBU is employed as the signal whose level is altered only during the self-refresh time period.
An operation of a DRAM circuit controlled by signal ZBBU will be described hereinafter.
In general, a partial activation operation is employed in a DRAM for the purpose of reducing consumption power. The number of partitioned blocks are apt to be increased together with increase of the storage capacity. However, advance in the partitioned operation will result in a greater number of refresh cycles (the number of refresh operations required to refresh all the memory cells on the chip).
Increase in the memory capacity has resulted in a lower absolute value of the capacitance of the memory cell capacitor. Leakage current of a capacitor in a memory cell is increased due to various elements such as a thinner dielectric film of a capacitor, degradation of the subthreshold characteristics of an access transistor, and closer distance between each memory cell. The tendency of degradation in refresh characteristics of a memory (implies the duration of time where data can be maintained in a memory cell without a refresh operation) is noticeable.
It is therefore desirable to minimize the number of refresh cycles. For the purpose of reducing the operating current during a self refresh operation and reducing the number of refresh cycles, an approach of operating more blocks during a self refresh operation than in a normal operation is taken.
FIG. 7 shows a structure of an DRAM divided into 8 blocks. Signal ZBBU is a self refresh mode signal and attains an L level during a self refresh operation. In a normal operation mode, signal ZBBU attains an H level whereby only one of the eight blocks selected by the block addresses Z.sub.0 -Z.sub.2 is selected by an appropriate one block address.
In a self refresh operation, signal ZBBU attains an L level, whereby two blocks out of the eight blocks are operated. When (Z.sub.2, Z.sub.1, Z.sub.0)=(0, 0, 0) for example, the outputs of OR circuits 508 and 528 attain an H level regardless of the value Z.sub.2 if signal ZBBU=L. Therefore, blocks (0, 0, 0) and (1, 0, 0) are selected at the same time.
Signal ZBBU is not limited to the above-described signal, and an operation similar to that described in the following can be implemented as long as the level is altered only during a self refresh period.
According to the second conventional implement shown in FIG. 6, a structure of applying an inverted version of signal ZBBU by inverter 218 to one input terminal of NOR circuit 216 allows NOR circuit 216 to be constantly closed regardless of the level signal EXTZWE.
More specifically, since P channel MOS transistor 220 in FIG. 11 is closed during a self refresh period, no through current flows through NOR circuit 216 even if signal EXTZWE attains an intermediate level.
However, a conventional input buffer circuit of the above-described structure receiving an input/output control signal has a problem that there is a possibility of generation of a through current therein when the DRAM attains a stand-by state, i.e. when signals /RAS and /CAS both attain an H level and the level of other input pins is arbitrary.